1. Technical Field
The present disclosure relates to a wiring board, a method of manufacturing the same, and a semiconductor device having the wiring board, and more particularly to a wiring board formed as a coreless structure (a structure without a core substrate), a method of manufacturing the same, and a semiconductor device having the wiring board.
2. Related Art
In the related art wiring boards, there has been known coreless boards whose thickness can be reduced by eliminating a core substrate. For instance, a semiconductor device 200 shown in FIG. 1 has been known as a semiconductor device in which electronic components are mounted on the coreless board.
FIG. 1 is a cross-sectional view of a related-art semiconductor device.
By reference to FIG. 1, the related-art semiconductor device 200 has a wiring board 201 serving as a coreless board; electronic components 202 and 203; and an external connection terminal 204.
The wiring board 201 has laminated insulating layers 211, 217, and 221; pads 212 and 213; wiring patterns 215, 216, 218, and 219; vias 222 and 226; external connection pads 223 and 227; and solder resists 231 and 232.
The insulating layer 211 is a layer in which the pads 212 and 213 to which the electronic components 202 and 203 are connected are formed. The pads 212 are provided on a surface 211A (a surface of the insulating layer 211 on which the electronic components 202 and 203 are mounted) of the insulating layer 211 such that side surfaces of the respective pads 212 are covered with the insulating layer 211. Each of the pads 212 has a multilayer structure consisting of an Au layer 241 and an Ni layer 242. The pads 212 are formed such that a surface 241A of the Au layer 241 becomes essentially flush with the surface 211A of the insulating layer 211. A bump 206 is disposed on the Au layer 241 of each of the pads 212. The pads 212 are electrically connected to the electronic component 202 via the bumps 206.
The pads 213 are provided on the surface 211A of the insulating layer 211 such that side surfaces of the pads 213 are covered with the insulating layer 211. Each of the pads 213 has a multilayer structure consisting of the Au layer 241 and the Ni layer 242. The pads 213 are formed such that the surface 241A of the Au layer 241 becomes essentially flush with the surface 211A of the insulating layer 211. The electronic component 203 is connected to the Au layer 241 of each of the pads 213.
Each of the wiring patterns 215 has a via 244 and a wire 245. The vias 244 are provided so as to penetrate through portions of the insulating layer 211 facing the pads 212. The vias 244 are connected to the pads 212. The wires 245 are formed integrally with the vias 244 and provided on a surface 211B (a surface of the insulating layer 211 opposite to the surface 211A) of the insulating layer 211. The wires 245 are electrically connected to the pads 212 via the vias 244.
Each of the wiring patterns 216 has a via 246 and a wire 247. The vias 246 are provided so as to penetrate through portions of the insulating layer 211 facing the pads 213. The vias 246 are connected to the pads 213. The wires 247 are formed integrally with the vias 246 and provided on the surface 211B of the insulating layer 211. The wires 247 are electrically connected to the pads 213 via the vias 246.
The insulating layer 217 is provided on the surface 211B of the insulating layer 211 so as to cover portions of the wires 245 and 247. Each of the wiring patterns 218 has a via 251 and a wire 252. The vias 251 are provided so as to penetrate through portions of the insulating layer 217 facing the wires 245. The vias 251 are electrically connected to the wires 245. The wires 252 are formed integrally with the vias 251 and provided on the surface 217B of the insulating layer 217 (a surface of the insulating layer 217 on which the insulating layer 221 is provided). The wiring patterns 218 configured above are electrically connected to the pads 212 via the wiring patterns 215.
Each of the wiring patterns 219 has a via 253 and a wire 254. The vias 253 are provided so as to penetrate through portions of the insulating layer 217 facing the wires 247. The vias 253 are connected to the wires 247. The wires 254 are formed integrally with the vias 253 and provided on the surface 217B of the insulating layer 217. The wiring patterns 219 configured above are electrically connected to the pads 213 via the wiring patterns 216.
The insulating layer 221 is provided on the surface 217B of the insulating layer 217 so as to cover portions of the wires 252 and 254. The vias 222 are provided so as to penetrate through portions of the insulating layer 221 facing the wires 252. The vias 222 are connected to the wires 252. The external connection pads 223 are formed integrally with the vias 222 and provided on a surface 221B of the insulating layer 221 (a surface of the insulating layer 221 on which a solder resist 232 is provided).
The vias 226 are provided so as to penetrate through portions of the insulating layer 221 opposing the wires 254. The vias 226 are connected to the wires 254. The external connection pads 227 are formed integrally with the vias 226 and provided on the surface 221B of the insulating layer 221.
The solder resist 231 is provided so as to cover the surface 211A of the insulating layer 211. Each of the solder resists 231 has an opening 231A from which the pad 212 is to be exposed and an opening 231B from which the pad 213 is to be exposed.
The solder resist 232 is provided so as to cover the surface 221B of the insulating layer 221. Each of the solder resists 232 has an opening 232A from which the external connection pad 223 is to be exposed and an opening 232B from which the external connection pad 227 is to be exposed.
The electronic component 202 is connected to the pads 212 via the bumps 206. Thereby, the electronic component 202 is electrically connected to the pads 212. An underfill resin 207 is filled between the electronic component 202 and the wiring board 201.
The electronic component 203 is fixed onto the pads 213 by means of the solder 208. The electronic component 203 is electrically connected to the pads 213. The external connection terminals 204 are provided on the external connection pads 223 and 227 exposed from the openings 232A and 232B.
The external connection terminals 204 are provided on the external connection pads 223 and 227. The external connection terminals 204 are terminals connected to pads provided on a mounting board (not shown), such as a mother board.
When a thickness M1′ of a portion which includes solder resist 231 and insulating layers 211, 217, 221 is set from 200 μm to 300 μm, a thickness M2′ of the solder resist 232 may be set from 20 μm to 50 μm, for example.
As described above, the electronic components 202 and 203 are mounted on the wiring board 201 serving as a coreless board, so that the size of the semiconductor device 200 in thickness direction can be reduced (see e.g., JP-A-2000-323613).
In the related art wiring board 201, the size of the wiring board 201 in the thickness direction can be reduced. However, since there is no core substrate serving as a support board for supporting the laminated insulating layers 211, 217, and 221, there is a problem that warpage is likely to arise.
Specifically, when warpage of the wiring board 201 is large, it is very hard to connect (mount) the electronic components 202 and 203 onto the pads 212 and 213 of the wiring board 201 with a high accuracy, and thus a connection failure between the electronic components 202 and 203 and the wiring board 201 occurs. Further, it is very hard to connect (mount) the external connection terminal 204 of the wiring board 201 onto pads of a mounting board (not shown) such as a mother board, with a high accuracy, and thus a connection failure between the wiring board 201 and the mount board occurs.